The present invention is related to a stacked leaded array. More specifically, the present invention is related to stacked electronic components, including tabbed and multi-layered ceramic capacitors (MLCCs), in a common array for improved volumetric efficiency and functionality improvements in a circuit of a given volume.
Miniaturization is an ongoing effort in electronic circuit and component design. These efforts are particularly relevant in the design of capacitors since capacitance is a function of the overlap area between internal electrodes of opposed polarity as well as the thickness and permittivity of the dielectric material between them. The capacitance per unit of volume of the individual capacitor can therefore be increased using a higher overlap area combined with thinner dielectric or increasing the permittivity of the dielectric.
However, there are two primary approaches to miniaturization. One approach is to miniaturize the individual components as described above. This approach has achieved great benefits yet the ability to further miniaturize the components requires significant technical discovery. The second approach is to increase functionality within a given volume. This approach requires significant advances in component interconnectivity and packaging.
The present invention provides significant advances in circuit miniaturization by stacking components, particularly MLCCs and other passive components, into a stacked array thereby improving the overall volumetric efficiency. By combining thinner components in a stacked leaded array the surface area required for mounting in the circuit is reduced whilst remaining within the maximum height requirements so improving overall volumetric efficiency.